Field of the Invention
The present invention generally relates to general purpose digital data processing systems, and more particularly relates to such systems that employ redirect or jump commands for instruction processors.
Description of the Prior Art
A key requirement of data processing systems is the ability, through instruction commands, to redirect the flow of machine execution. When processing instructions, instruction processors are often faced with a conditional jump to a non-sequential address, where the jump is based on the outcome of a calculation or another result. In addition, an interrupt can result in an instruction processor jumping to an unsequential address for the next instruction to process. Digital data processing systems often utilize a wide variety of non-jump redirection instructions other than conditional jump instructions which redirect the instruction processor execution. For example, the Unisys ITASCA data processing system has eight instructions and forty-three types of interrupts that can result in redirected instruction processor execution. Data processing systems typically utilize specialized "redirection" logic to support this variety of redirect commands.
Often times the redirection logic in data processing systems utilize a "dual path" logic design to redirect instruction processor execution in order to increase the performance of the instruction execution pipeline. In typical digital data processing systems, instructions are clocked out of an instruction cache into a normal instruction incrementation register. This register typically holds the instruction fetched from the cache by incrementing an address used in a previous fetch. The instruction is then gated through a multiplexer into the instruction pipeline. Once in the instruction pipeline, the instruction is gated through additional predecode and decode registers where the instruction decode begins. When an execution redirection occurs, such as with a conditional jump instruction or a non-jump redirection instruction, an alternate instruction path is selected. A feedback line, such as a jump active line, is set which switches the multiplexer to select a jump target register for the alternate instruction path, rather than the instruction normal execution register. Since the jump target register holds the instruction fetched from the jump target address, this new jump target instruction can be gated into the decode register so that execution can begin with a new instruction stream. The execution continues until the execution is once again redirected.
The dual path design has been used due to enhanced system performance and efficiency. For example, once a decision is made to take a jump, both the jump target instruction and the next instruction in the current instruction stream are already available from the instruction processor instruction cache. There are, however, many inherent disadvantages due to the hardware design having to accommodate both conditional jump instructions and non-jump redirection instructions. First, many of the hardware sequences required for normal conditional jump instructions are unnecessary with non-jump redirection instructions. It is often necessary to execute more complex instructions which perform other tasks other than simply redirecting the execution flow. As a result, hardware logic which simply facilitates redirection may not efficiently perform these other tasks which can include the loading of registers. Often times the designated base registers, which are coupled to instruction decodes and which typically are loaded with predetermined data before a jump is executed, can change in unpredictable ways. This unfortunately can invalidate an otherwise valid jump active signal. It may also not be known if a conditional branch instruction will in fact change the normal sequential execution of the instructions until the third stage (the arithmetic operation stage) of the instruction pipeline. A sequence consisting of an operand fetch may be initiated during the second stage of the pipeline in order to determine whether a jump should be taken during the arithmetic operation or third stage. When executing non-jump redirection instructions, the initiation of these sequences are not necessary and can result in the unintentional corruption of the prefetch instruction pipeline. Thus, when executing a non-jump redirection instruction, pseudo jump instructions must be used in order to accommodate the hardware design. Inputs to the instruction decode registers, which determine whether or not a jump is being taken, are forced to mimic a jump instruction to start hardware sequences which redirect execution in the instruction cache and address generation logic. In addition, special logic must be used to block unnecessary hardware sequences initiated by the pseudo jump instruction.